Introduction

What is this course about?

• The process of building a System on Chip (SoC)
• Focus on implementation process
  • Lectures move towards ASIC process
  • Laboratories use FPGA

What does it involve?

• 11 lectures + exam. (50% of marks)
  • Hopefully including a ‘guest spot’
  • Higher level coverage of processes and technology
• 11 laboratories (50% of marks)
  • Detailed work in most important parts of flow

What should you get from it?

• A flavour of the processes involved in translating a design model to a product
• A first hearing of some of the associated jargon
• If all goes well, a working system on chip

Systems on Chip

• A modern (2025) chip may have ~10¹¹ or more transistors
  • Slightly misleading in that – in many applications – many of these form RAM
  • Apple M2 Ultra has 134×10⁹ transistors on two dice
• A rough estimate of the largest FPGA capacity (contemporary) is ~10⁹ ‘ASIC transistors’
  • …plus blocks of RAM
  • Most designs won't be able to exploit all of them
  • Actual transistor count > 20 billion (2015)
• Hand-waving, very approximate estimates:
  • ASIC — maybe 1 billion?
  • FPGA — hundreds of millions?
• Design/manufacturing costs
  • Design is done in (big) teams whose outputs must integrate. cost hundreds of engineers @ >k$100/year ⇒ tens of M$10/year
  • CAD tools probably something similar to manpower costs
  • Mask making a few M$ for a state-of-the-art process

Gate cost is negligible. Design cost is not!

Module objectives

• A little more practice in digital design, especially in Verilog/SystemVerilog.
• A closer look at design flows
  • Including some more tools
• Instil/reinforce some general engineering design skills:
  • Modelling
  • Test/debug
  • Version control/regression
• Conform with pre-existing interfaces.
  • Be one designer in a SoC building ‘team’
• A look at the underlying silicon technology.
  • ASICs
  • FPGAs
• To give a taste of some of the issues involved in silicon production.
• Gain an appreciation of the chip production process (& jargon!) and future trends.

Course Contents

• Lectures
  • Step through the implementation process
  • Where possible precede the corresponding lab. operation
  • Largely (but not exclusively) looking at ASIC production
• Practicals
  • Verilog implementation
  • Simulation
  • Debugging
  • Simulation
  • Timing
  • More simulation
  • Testing
  • Even more simulation
  • Compilation

The on-line contents is better!

Laboratory

The ‘team’ objective:

• Produce a GPU (Graphics Processing Unit) capable of drawing/plotting a range of functions on a display.
  • Functions are built as programmable hardware for speed
• Will be implemented on FPGA

Your objective:

• Produce one functional block
• Test & verify the interfaces
• Verify its function
• Integrate into an SoC
• Demonstrate

Practicals

The practical work is divided into four phases:

• Understand the interfaces and develop a test strategy
  • We supply some faulty units for diagnosis
• Develop a functional block and verify it in isolation
  • Leverage the interface tests to ensure system compatibility
• Integrate your block with the system, testing in an SoC environment
  • We supply the other parts of the SoC: system-level simulation
• Synthesize the logic: demonstrate the system operating under software control
  • Real pictures!

This is all described in the laboratory manual.

• Next set of notes.
• Back to contents.