Code style

Decade counter timing

Example: decade counter

Desired behaviour:

Objective: enable next clock edge when state reaches ‘9’


Decade counter timing

Alternatives:

always @ (posedge clk)
  if (count < 9) count <= count + 1;
  else           count <= 0;
 
  assign rc = (count == 9);


Decade counter timing

or

always @ (posedge clk)
if (count < 9) count <= count + 1;
else           count <= 0;
 
always @ (posedge clk) rc <= (count == 8);
                                     NOTE!


The second example will generate an output (slightly) sooner and without glitching.

Up/back to Tradeoffs.

Forwards to FSMs.