Initialisation

When a state-holding element is switched on it will settle into a stable state.

It is not predictable what state this will be, so it is unknown.

Does this matter? In some cases it does, in others it doesn't.

Example: RISC-V registers

• X1-X31 are undefined
• PC is defined (to an arbitrary value: we use 00000000)
• Privilege mode must be set to ‘Machine’

I.e. only the essential values are cleared Rule of thumb:

• Control registers should be initialised
• Data registers probably don't need initialisation

Undefined (“unknown”) values tend to propagate through logic.

This is usually a good thing as it acts as a warning that something is wrong. Learn to exploit them!

Reset signals

The question of whether to include a reset on a flip-flop has no simple answer.

• The inclusion of reset logic imposes a small power/area penalty on a flip-flop.
• The fan-out of the reset network is typically very large and consumes some resources.
• Failing to reset a flip-flop which needs to be defined can be catastrophic.

Case: consider a clock divider flip-flop:

As a circuit this will function because it is in some digital state and will toggle to the other when clocked.

In simulation it will start unknown and always remain that way.

In Verilog you could ‘cure’ this anomaly with an ‘initial’; but if that is accidentally done to something where the phase matters then it's doom again.

In general:

• data registers can tolerate starting undefined
• control registers should be reset
  • this would include ‘validity’ indicators on data etc.

Some designers prefer to reset every flip-flop as a matter of routine.
(There is a small additional cost in size and speed.)

You have to decide which approach works for you.

Memories

RAM does not have reset. If you expect a RAM to contain some values (typically zeroes) you will have to write these in actively.

• This is easy in a RAM model with a ‘for’ loop.
• This is considerable effort in reality requiring an FSM … and time.

Resetting in ASICs

Some form of reset signal is vital, at least for a subset of the flip-flops. These are primarily those concerned with control state. Without a reset flip-flops will power-up in an unknown state.

In a physical circuit it may be that (e.g.) an FSM will ‘naturally’ progress into a stable state (like an ‘idle’ state) and await legitimate input — and it makes sense to design it this way. However this will not help in simulation and you do need to verify your designs!

Resetting in FPGAs

The state of an FPGA is downloaded when it is configured. This means:

• flip-flops will be initialised
• memory contents will be defined

This means, for example:

• ‘initial’ will work and a register can be preset at t = 0
• a memory (on chip) can be initialised with ‘$readmemh()’

The second of these allows the creation of on-chip ROMs, useful (for example) in bootstrapping a processor or providing look-up tables.

Note that these facilities are provided because of the particular FPGA characteristics. They would not be available on an ASIC.

The ‘unknown’ state in simulators

Unknown/undefined states are a characteristic of digital simulation. Verilog simulation is digital, with signals adopting states {‘0’, ‘1’, ‘x’, ‘z’} and these have well-defined operations. For example:

0 && x == 0
1 && x == x

Digital (functional) simulation does not represent intermediate states, transition (edge) speeds etc.

Not all simulators work this way. Circuit-level simulators represent the analogue voltages on the wires to give more accurate estimates of the behaviour of the implementation. These values are (in principle) continuous, therefore always ‘known’, therefore they have to be assumed at start-up.

Unknown values will not appear. However the assumed values may not be those which occur in a real circuit and therefore should not be relied on.

This is another good reason for running a functional simulation as part of the design flow.

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