Simulation is part of modelling; the accuracy of the model is refined as the design process progresses.
Caveat: The intention of this material is to give enough information to facilitate design. It is not intended to be a complete description of all the available facilities.
“A little inaccuracy sometimes saves tons of explanation.”
Saki, The Square Egg (1924)
The purpose of simulation is to verify that, when you build something, it will work. First time and every time. It is widely practised in engineering when something expensive or potentially dangerous is being built. Examples include:
Simulation is used at a number of levels from the design concept to the electrical (and, often, thermal) properties of the final product. In practice this may not stop at the chip level as these properties are also important in larger structures, up to complete systems.
Simulation gives the ability to determine the properties of a proposed system under a set of potential operating conditions. Remember – it only gives an approximation to ‘reality’ within the limits of the model used; this can still be very useful.
There is a trade-off between the accuracy of the model and the effort required to produce it. In our case this usually means that more accurate simulation takes longer and requires more expensive computers with more memory, file-store, etc. Therefore there is usually a pragmatic compromise on accuracy at various stages of development.
One big advantage of simulation is that the model gives observability. Consider building a chip, ignoring the time and cost of manufacture for the moment. If something is wrong then is it possible to diagnose the fault from the outside? This may be feasible in a simple, combinatorial device this becomes difficult once there is hidden state. At the System-on-Chip (SoC) scale then this is effectively impossible.
Simulated models allow otherwise hidden nodes to be examined so that problems can be found much more easily. Particular areas which are suspect can be examined in fine detail.
To finalise an ASIC design a number of different ‘levels’ of simulation must be performed.
Each looks at different aspects of the design.
This section concentrates on functional verification.
The other aspects will be revisited later.
A high-level model (e.g. a TLM – Transaction Level Model) can demonstrate the feasibility of an architecture. It may be refined down to a cycle-accurate model – i.e. one in which each operation can be timed by counting clock cycles – but not (sensibly) much further.
There is then a need for translation into a behavioural model which is the function of a Hardware Description Language (HDL). A behavioural model may be just that – a model – or it may be a synthesizeable Register Transfer Level (RTL) description which will eventually be converted into hardware.
The translation process from TLM to RTL may be error-prone; there is also the possibility of discovering previously untested cases as the model is prepared in more detail. There is therefore a need for simulation tests at the behavioural level. These tests perform functional verification, i.e. they check that the logic does what it is intended to.
Functional tests do not guarantee that a resultant circuit will fulfil its requirements: for example the design may be too slow to be clocked sufficiently fast to meet real time requirements. Neither do they guarantee that the result will be constructable.
Functional tests typically use assumptions of synchronous behaviour and do not give any absolute timing information; elapsed time is measured in clock cycles. The designer may have a target clock speed in mind at this point; whether the design will achieve that is still unknown. Thus a design may do what it is intended to do but may not meet real-time requirements.
It is possible to annotate the HDL description with timing estimates to gain some idea of timing behaviour but these are necessarily imprecise. Circuit speed is greatly influenced by its physical properties which are not yet known.
Timing verification involves estimating and summing the various delays in an implementation to identify and isolate the critical path. This can only be achieved once a design has been synthesized into the target technology so that a netlist of gates, flip-flops etc. is available.
There are typically two phases to timing verification: pre- and post-layout. Having obtained a netlist, CAD tools can produce an estimate of the critical path delay. Modern tools are smart enough to try to factor in wiring loads as well as gate delays; however the true wiring delays are not yet known. This will give a moderately accurate guide to the maximum clock frequency. If the circuit is apparently too slow at this point it's ‘back to the drawing board’.
Post-layout synthesis depends on a netlist following the Place-And-Route (PAR) stage and has a better estimate of timing. As well as wiring delays, other factors such as the need to add buffers (electrical amplification) may have been introduced. The simulation model used may be more precise, too. All this means is that it takes longer and, if a problem is found here, it is more expensive to iterate the design again.
Another concern here are the ‘edge speeds’ – the time it takes to switch wires between digital states. An edge which is too slow harms circuit performance but is also more vulnerable to electrical noise inducing extra switching. Not all gates will have the same input threshold so a slow edge may apparently switch at different times when interpreted at different destinations.
A real circuit needs power, something neglected up to this point. When a gate switches its output there is a surge of charge onto or off a power supply. All these cause a (varying) current in the power supplies. There are (at least!) two serious concerns:
Are the wires big enough to handle the current? A too-small wire is a fuse and will blow! More likely, there may be a wire that's a bit thinner than is desirable which will ‘age’ due to electromigration and shorten the lifetime of the device.
The gate models assume a supply of a certain voltage. The power supplies carry current and have resistance, therefore will impose a voltage drop (Ohm's law). Thus the supply voltage at the centre of a chip (furthest from the connections) will be lower than that at the edges. The power supply wiring must be adequate to keep this drop within bounds for previous assumptions to remain valid. In case of difficulty, the usual solution is to force an increase in the number/width of the supply wires.
Of course the power that goes in comes out as heat. Thus there may be thermal modelling ... and so on ...