Events

Digital simulation is usually ‘event-driven’. The basic operation is described in this aside.

Events are awaited using the ‘#<value> @’ keyword.

• e.g. as part of a loop #<value> always @ (...)
• May be used anywhere in code

• A signal changing is an event @ (enable)
• These can be further refined @ (posedge clk)
• Other events can be created to aid simulation
  event my_event;
  -> my_event; // signal something
  ...
  always @ (my_event)
  ...
  

Waits for the next time the event is detected in the future.

Not a strict thread rendezvous.

Events

Events are things that happen during execution; they can be used to control the progression of a test sequence. An event can be something like:

(posedge clk)

It is possible to wait for events within a test harness. The ‘@’ ‘keyword’ really means ‘wait until the following condition is satisfied’. This could be as simple as synchronising with the next clock cycle:

which will wait until the specified event occurs. These can be used in combination with other operators. For example:

Will wait for between zero and three (inclusive) rising edges of the clock.

User events

Events can also be declared and generated in a behavioural model. For example, here is a mechanism for generating reports when errors are detected:

event error; // Declare event

always @ (error) $display(“Error at time %t”, $time);

initial
begin
... // Simulation proceeds
if (<error condition>) -> error; // Generate event
...
end

Such signalling can be used to allow different blocks to interact in a test file. For example:

initial
begin
[Do reset sequencing]
-> reset_done;
end
initial
begin
@(reset_done)
[Start test sequence]
...
end

For more complete examples, try: http://www.asic-world.com/verilog/art_testbench_writing3.html

Up to simulation

Back to simulation time & delays

Forward initialising simulations