Miscellany

A collection of other timing-related issues.

Timing checking tools

A number of tools exist to assist with timing closure. Many of these are only appropriate when a physical realisation of the chip is available.

• Static Timing Analysis (STA)
• Edge speed analysis
• Hold time checking
• Clock skew analysis
• …

Tools

A Static Timing Analyser (introduced earlier) will give an estimate of the critical path in a system by searching all paths between clocked registers and finding the slowest. This then sets the ‘standard’ for other logic speeds; there is (usually) no point in optimising any logic paths already faster than the critical path.

The delay of the critical path will depend on the number of serial logic gates, their type, the fanout and other factors affecting the electrical load (particularly wire lengths) and their output impedance or ‘drive strength’. All these factors go into ‘the mix’ when attempting to optimise the circuit.

Typically, synthesis tools will have options which allow the engineer to put more importance on speed, size, power etc. It may be that a circuit can be optimised for speed but this may result in it being larger or more power hungry.

Edge speeds are the time it takes a digital circuit to switch between states. They depend on the outputting gates drive and the (capacitive) load it needs to switch. Edges which are ‘too slow’ may introduce problems such as:

• induced noise near the threshold may be received and amplified.
• different target gates may ‘see’ the input switch at (significantly) different times.
• increased time spent near the ‘half way’ level may result in an extra power drain.

Tools are available to identify any slow^† edges, possibly for further attention.

^†The user can define what “slow” means.

The behavioural simulators used for functional verification are not the only class of circuit simulators. At the most detailed level are simulators which model the parameters of each transistor and solve differential equations: these are typically generically referred to as ‘SPICE although this is really only one of the families of software^†. Rather than logic levels these model analogue voltages.

^†Like ‘Hoover’ for ‘vacuum cleaner’.

The modelling in such precise detail gives very good answers but takes a lot of computation. Therefore such modelling is usually confined to small units such as standard cells (q.v.).

There are also simulators which approximate the analogue behaviour more cheaply (but less accurately). These can be used to produce good timing models (especially from post-layout netlists) since they are modelling the gates' ‘drive’ and the wires' ‘load’, revealing signal edge speeds etc. They are still slower than a simple, digital model for functionality.

Note that a potential disadvantage of an analogue simulation is that the signals are always represented by a voltage: there is no concept of ‘unknown’ (X) values which can sometimes be useful in fault-finding.

With ‘challenging’ speed targets a flip-flop may be designed with a data hold time longer than its propagation delay. With such it would be dangerous to connect one flip-flop output directly to another's input. Any logic in-between will naturally act as an additional delay and help meet the true constraints. Hold-time checking will identify any remaining risks here and allow extra buffer insertion.

Remember that problems with a too-long critical path may be accommodated by reducing the clock frequency. Hold-time problems are a property of the circuit and there is no cure if they appear in the chip!

Delay lines

It is possible – and sometimes necessary – to build delays onto ASICs. An approximate delay can be produced with a ‘chain’ of inverters or buffers; the actual delay on a given design and process may vary by a factor of two or more depending on the manufacturing and operation conditions of the chip.

Precise delays need to be calibrated against a reliable reference frequency. These are typically chains of gates (as above) whose length can be altered (e.g. by multiplexing output taps) to give the nearest available approximation to the required delay. Periodic recalibration may be needed due to thermal drift.

An example would be a Delay-Locked Loop (DLL). For instance Xilinx FPGAs contain a small number of DLLs which allow the insertion of a known delay. A typical application is to delay a clock signal so that edges at the leaves of the distribution tree are in phase (via a total delay of a number of clock cycles) with an incoming reference. This effectively ‘removes’ the clock buffer delays.

Delays are often needed in communication, such as between chips. A common application is in SDRAM interfacing where the RAM's clock is sourced by the master interface, delayed across the circuit board, through the RAM and back across the board again. This means returning data has a well-defined frequency but an ill-defined phase. Delays are used to bring received signals bak into phase with the internal clock. (The delays also need adjusting dynamically as the temperature (etc.) varies too.)

Some random curiousities

Up to Clocking.

Back to clock generation.

Forwards to Interconnection.