c.1977 First HDLs developed
1985 Verilog introduced by Gateway Design Automation
1990 Gateway purchased by Cadence Design Systems
1991 ‘Opened’ as a language
1995 Made into IEEE standard #1364
2001 Second IEEE standard including extensions and improvements
2005 A new standard with some minor improvements
2005 SystemVerilog introduced: Verilog-2005 plus major
extensions ⇒ IEEE #1800
2009 SystemVerilog IEEE Std. 1800-2009 which merges 1364-2005 and
1800-2005 (stable release 2017)
2012 SystemVerilog #1800-2012
2017 SystemVerilog #1800-2017
2023 SystemVerilog #1800-2023
The version used in this module is … fairly up-to-date. (It moves with the tool upgrades.) Much of the infrastructure is compliant with older, Verilog standards but we've upgraded the parts you work with directly. You can choose what you use.
SystemVerilog is overtaking Verilog in popularity (remember it's a superset) but there is still a lot of older Verilog code ‘out there’.
A lot of the information in this module is based on Verilog-2001. This is still common although the superset, SystemVerilog, is replacing this.
Verilog was designed as a HDL – a Hardware Description Language –. It was not orignially intended to be a hardware design tool although a significant subset is now very widely used to specify circuits at RTL and above. A wider range of constructs are useful in hardware verification and this is vital in the production of working designs.
These pages cover some of the significant differences in the major versions. Verilog-95 is becoming obsolescent. Examples of features absent include:
This is not an exhaustive list; rather it is intended to be indicative of the type of enhancements. Verilog-2001 is backwards compatible.
Some of these features may be unfamiliar, at least in Verilog, the first time you read this. You don't need to use them, although there will be some brief coverage, shortly.
Because Verilog syntax has evolved from (arguably) crude beginnings but maintained backward compatibility there are sometimes multiple ways to specify the same thing. The choice of structure will be influenced by the author's stylistic prejudices. The best advice is to try and make things as simple and obvious as you can. Sometimes there is an ‘obviously better’ way but, like any piece of composition, sometimes it's the author's preferred style.
wire p; assign p = !a; // This?
reg q; always @ (a) q = !a; // or this?
module inv1(input wire a, output wire q);
assign q = !a;
endmodule;
module inv2(a, q);
input a;
output q;
wire a, q;
assign q = ~a;
endmodule;
Both these modules have the same effect.
SystemVerilog attempts to combine the merits of Verilog HDL with a Hardware Verification Language (HVL). It is somewhat C++-like. Some more features of SystemVerilog are expanded on here.
A selection of additional features includes:
Other ‘existing’ Verilog features have also been enhanced/regularised in places. Some of these features are for synthesizable RTL code, others are there to improve the modelling and verification features.
The current standard is 2023; not all toolsets have caught up with this yet.
We are gradually converting to SystemVerilog in our labs. (2025); the
plan is to use this as the HDL of choice from the first year. You may
or may not have used it before. In COMP32211 we now support
SystemVerilog for both simulation (testbenches, verification) and
synthesis to FPGA.
We clearly haven't had time to try everything yet but you
should find most, if not all, features work. However not all staff
will be ‘expert’ yet!
VHDL is a different HDL which has some popularity. In principle it works largely in the same way as Verilog. It has some advantages, such as stronger typing, and disadvantages, such as verbosity. However converting from one to the other is largely a matter of new syntax.
Verilog is probably more widely used than VHDL worldwide (including UK & USA, China) although VHDL is more dominant in several European countries.
For further opinions there are numerous VHDL vs. Verilog discussions out there in Internet Land.